Line data Source code
1 : /*
2 : * Copyright (C) 2007-2024 Free Software Foundation, Inc.
3 : *
4 : * This file is free software; you can redistribute it and/or modify it
5 : * under the terms of the GNU General Public License as published by the
6 : * Free Software Foundation; either version 3, or (at your option) any
7 : * later version.
8 : *
9 : * This file is distributed in the hope that it will be useful, but
10 : * WITHOUT ANY WARRANTY; without even the implied warranty of
11 : * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 : * General Public License for more details.
13 : *
14 : * Under Section 7 of GPL version 3, you are granted additional
15 : * permissions described in the GCC Runtime Library Exception, version
16 : * 3.1, as published by the Free Software Foundation.
17 : *
18 : * You should have received a copy of the GNU General Public License and
19 : * a copy of the GCC Runtime Library Exception along with this program;
20 : * see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
21 : * <http://www.gnu.org/licenses/>.
22 : */
23 :
24 : #ifndef _CPUID_H_INCLUDED
25 : #define _CPUID_H_INCLUDED
26 :
27 : /* %ecx */
28 : #define bit_SSE3 (1 << 0)
29 : #define bit_PCLMUL (1 << 1)
30 : #define bit_LZCNT (1 << 5)
31 : #define bit_SSSE3 (1 << 9)
32 : #define bit_FMA (1 << 12)
33 : #define bit_CMPXCHG16B (1 << 13)
34 : #define bit_SSE4_1 (1 << 19)
35 : #define bit_SSE4_2 (1 << 20)
36 : #define bit_MOVBE (1 << 22)
37 : #define bit_POPCNT (1 << 23)
38 : #define bit_AES (1 << 25)
39 : #define bit_XSAVE (1 << 26)
40 : #define bit_OSXSAVE (1 << 27)
41 : #define bit_AVX (1 << 28)
42 : #define bit_F16C (1 << 29)
43 : #define bit_RDRND (1 << 30)
44 :
45 : /* %edx */
46 : #define bit_CMPXCHG8B (1 << 8)
47 : #define bit_CMOV (1 << 15)
48 : #define bit_MMX (1 << 23)
49 : #define bit_FXSAVE (1 << 24)
50 : #define bit_SSE (1 << 25)
51 : #define bit_SSE2 (1 << 26)
52 :
53 : /* Extended Features (%eax == 0x80000001) */
54 : /* %ecx */
55 : #define bit_LAHF_LM (1 << 0)
56 : #define bit_ABM (1 << 5)
57 : #define bit_SSE4a (1 << 6)
58 : #define bit_PRFCHW (1 << 8)
59 : #define bit_XOP (1 << 11)
60 : #define bit_LWP (1 << 15)
61 : #define bit_FMA4 (1 << 16)
62 : #define bit_TBM (1 << 21)
63 : #define bit_MWAITX (1 << 29)
64 :
65 : /* %edx */
66 : #define bit_MMXEXT (1 << 22)
67 : #define bit_LM (1 << 29)
68 : #define bit_3DNOWP (1 << 30)
69 : #define bit_3DNOW (1u << 31)
70 :
71 : /* %ebx */
72 : #define bit_CLZERO (1 << 0)
73 : #define bit_WBNOINVD (1 << 9)
74 :
75 : /* Extended Features Leaf (%eax == 7, %ecx == 0) */
76 : /* %ebx */
77 : #define bit_FSGSBASE (1 << 0)
78 : #define bit_SGX (1 << 2)
79 : #define bit_BMI (1 << 3)
80 : #define bit_HLE (1 << 4)
81 : #define bit_AVX2 (1 << 5)
82 : #define bit_BMI2 (1 << 8)
83 : #define bit_RTM (1 << 11)
84 : #define bit_AVX512F (1 << 16)
85 : #define bit_AVX512DQ (1 << 17)
86 : #define bit_RDSEED (1 << 18)
87 : #define bit_ADX (1 << 19)
88 : #define bit_AVX512IFMA (1 << 21)
89 : #define bit_CLFLUSHOPT (1 << 23)
90 : #define bit_CLWB (1 << 24)
91 : #define bit_AVX512PF (1 << 26)
92 : #define bit_AVX512ER (1 << 27)
93 : #define bit_AVX512CD (1 << 28)
94 : #define bit_SHA (1 << 29)
95 : #define bit_AVX512BW (1 << 30)
96 : #define bit_AVX512VL (1u << 31)
97 :
98 : /* %ecx */
99 : #define bit_PREFETCHWT1 (1 << 0)
100 : #define bit_AVX512VBMI (1 << 1)
101 : #define bit_PKU (1 << 3)
102 : #define bit_OSPKE (1 << 4)
103 : #define bit_WAITPKG (1 << 5)
104 : #define bit_AVX512VBMI2 (1 << 6)
105 : #define bit_SHSTK (1 << 7)
106 : #define bit_GFNI (1 << 8)
107 : #define bit_VAES (1 << 9)
108 : #define bit_VPCLMULQDQ (1 << 10)
109 : #define bit_AVX512VNNI (1 << 11)
110 : #define bit_AVX512BITALG (1 << 12)
111 : #define bit_AVX512VPOPCNTDQ (1 << 14)
112 : #define bit_RDPID (1 << 22)
113 : #define bit_KL (1 << 23)
114 : #define bit_CLDEMOTE (1 << 25)
115 : #define bit_MOVDIRI (1 << 27)
116 : #define bit_MOVDIR64B (1 << 28)
117 : #define bit_ENQCMD (1 << 29)
118 :
119 : /* %edx */
120 : #define bit_AVX5124VNNIW (1 << 2)
121 : #define bit_AVX5124FMAPS (1 << 3)
122 : #define bit_UINTR (1 << 5)
123 : #define bit_AVX512VP2INTERSECT (1 << 8)
124 : #define bit_SERIALIZE (1 << 14)
125 : #define bit_TSXLDTRK (1 << 16)
126 : #define bit_PCONFIG (1 << 18)
127 : #define bit_IBT (1 << 20)
128 : #define bit_AMX_BF16 (1 << 22)
129 : #define bit_AVX512FP16 (1 << 23)
130 : #define bit_AMX_TILE (1 << 24)
131 : #define bit_AMX_INT8 (1 << 25)
132 :
133 : /* Extended Features Sub-leaf (%eax == 7, %ecx == 1) */
134 : /* %eax */
135 : #define bit_SHA512 (1 << 0)
136 : #define bit_SM3 (1 << 1)
137 : #define bit_SM4 (1 << 2)
138 : #define bit_RAOINT (1 << 3)
139 : #define bit_AVXVNNI (1 << 4)
140 : #define bit_AVX512BF16 (1 << 5)
141 : #define bit_CMPCCXADD (1 << 7)
142 : #define bit_AMX_COMPLEX (1 << 8)
143 : #define bit_AMX_FP16 (1 << 21)
144 : #define bit_HRESET (1 << 22)
145 : #define bit_AVXIFMA (1 << 23)
146 :
147 : /* %edx */
148 : #define bit_AVXVNNIINT8 (1 << 4)
149 : #define bit_AVXNECONVERT (1 << 5)
150 : #define bit_AVXVNNIINT16 (1 << 10)
151 : #define bit_PREFETCHI (1 << 14)
152 : #define bit_USER_MSR (1 << 15)
153 : #define bit_AVX10 (1 << 19)
154 : #define bit_APX_F (1 << 21)
155 :
156 : /* Extended State Enumeration Sub-leaf (%eax == 0xd, %ecx == 1) */
157 : #define bit_XSAVEOPT (1 << 0)
158 : #define bit_XSAVEC (1 << 1)
159 : #define bit_XSAVES (1 << 3)
160 :
161 : /* PT sub leaf (%eax == 0x14, %ecx == 0) */
162 : /* %ebx */
163 : #define bit_PTWRITE (1 << 4)
164 :
165 : /* Keylocker leaf (%eax == 0x19) */
166 : /* %ebx */
167 : #define bit_AESKLE ( 1<<0 )
168 : #define bit_WIDEKL ( 1<<2 )
169 :
170 : /* AVX10 sub leaf (%eax == 0x24) */
171 : /* %ebx */
172 : #define bit_AVX10_256 (1 << 17)
173 : #define bit_AVX10_512 (1 << 18)
174 :
175 : /* Signatures for different CPU implementations as returned in uses
176 : of cpuid with level 0. */
177 : #define signature_AMD_ebx 0x68747541
178 : #define signature_AMD_ecx 0x444d4163
179 : #define signature_AMD_edx 0x69746e65
180 :
181 : #define signature_CENTAUR_ebx 0x746e6543
182 : #define signature_CENTAUR_ecx 0x736c7561
183 : #define signature_CENTAUR_edx 0x48727561
184 :
185 : #define signature_CYRIX_ebx 0x69727943
186 : #define signature_CYRIX_ecx 0x64616574
187 : #define signature_CYRIX_edx 0x736e4978
188 :
189 : #define signature_INTEL_ebx 0x756e6547
190 : #define signature_INTEL_ecx 0x6c65746e
191 : #define signature_INTEL_edx 0x49656e69
192 :
193 : #define signature_TM1_ebx 0x6e617254
194 : #define signature_TM1_ecx 0x55504361
195 : #define signature_TM1_edx 0x74656d73
196 :
197 : #define signature_TM2_ebx 0x756e6547
198 : #define signature_TM2_ecx 0x3638784d
199 : #define signature_TM2_edx 0x54656e69
200 :
201 : #define signature_NSC_ebx 0x646f6547
202 : #define signature_NSC_ecx 0x43534e20
203 : #define signature_NSC_edx 0x79622065
204 :
205 : #define signature_NEXGEN_ebx 0x4778654e
206 : #define signature_NEXGEN_ecx 0x6e657669
207 : #define signature_NEXGEN_edx 0x72446e65
208 :
209 : #define signature_RISE_ebx 0x65736952
210 : #define signature_RISE_ecx 0x65736952
211 : #define signature_RISE_edx 0x65736952
212 :
213 : #define signature_SIS_ebx 0x20536953
214 : #define signature_SIS_ecx 0x20536953
215 : #define signature_SIS_edx 0x20536953
216 :
217 : #define signature_UMC_ebx 0x20434d55
218 : #define signature_UMC_ecx 0x20434d55
219 : #define signature_UMC_edx 0x20434d55
220 :
221 : #define signature_VIA_ebx 0x20414956
222 : #define signature_VIA_ecx 0x20414956
223 : #define signature_VIA_edx 0x20414956
224 :
225 : #define signature_VORTEX_ebx 0x74726f56
226 : #define signature_VORTEX_ecx 0x436f5320
227 : #define signature_VORTEX_edx 0x36387865
228 :
229 : #define signature_SHANGHAI_ebx 0x68532020
230 : #define signature_SHANGHAI_ecx 0x20206961
231 : #define signature_SHANGHAI_edx 0x68676e61
232 :
233 : #ifndef __x86_64__
234 : /* At least one cpu (Winchip 2) does not set %ebx and %ecx
235 : for cpuid leaf 1. Forcibly zero the two registers before
236 : calling cpuid as a precaution. */
237 : #define __cpuid(level, a, b, c, d) \
238 : do { \
239 : if (__builtin_constant_p (level) && (level) != 1) \
240 : __asm__ __volatile__ ("cpuid\n\t" \
241 : : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
242 : : "0" (level)); \
243 : else \
244 : __asm__ __volatile__ ("cpuid\n\t" \
245 : : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
246 : : "0" (level), "1" (0), "2" (0)); \
247 : } while (0)
248 : #else
249 : #define __cpuid(level, a, b, c, d) \
250 : __asm__ __volatile__ ("cpuid\n\t" \
251 : : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
252 : : "0" (level))
253 : #endif
254 :
255 : #define __cpuid_count(level, count, a, b, c, d) \
256 : __asm__ __volatile__ ("cpuid\n\t" \
257 : : "=a" (a), "=b" (b), "=c" (c), "=d" (d) \
258 : : "0" (level), "2" (count))
259 :
260 :
261 : /* Return highest supported input value for cpuid instruction. ext can
262 : be either 0x0 or 0x80000000 to return highest supported value for
263 : basic or extended cpuid information. Function returns 0 if cpuid
264 : is not supported or whatever cpuid returns in eax register. If sig
265 : pointer is non-null, then first four bytes of the signature
266 : (as found in ebx register) are returned in location pointed by sig. */
267 :
268 : static __inline unsigned int
269 7227 : __get_cpuid_max (unsigned int __ext, unsigned int *__sig)
270 : {
271 : unsigned int __eax, __ebx, __ecx, __edx;
272 :
273 : #ifndef __x86_64__
274 : /* See if we can use cpuid. On AMD64 we always can. */
275 : #if __GNUC__ >= 3
276 : __asm__ ("pushf{l|d}\n\t"
277 : "pushf{l|d}\n\t"
278 : "pop{l}\t%0\n\t"
279 : "mov{l}\t{%0, %1|%1, %0}\n\t"
280 : "xor{l}\t{%2, %0|%0, %2}\n\t"
281 : "push{l}\t%0\n\t"
282 : "popf{l|d}\n\t"
283 : "pushf{l|d}\n\t"
284 : "pop{l}\t%0\n\t"
285 : "popf{l|d}\n\t"
286 : : "=&r" (__eax), "=&r" (__ebx)
287 : : "i" (0x00200000));
288 : #else
289 : /* Host GCCs older than 3.0 weren't supporting Intel asm syntax
290 : nor alternatives in i386 code. */
291 : __asm__ ("pushfl\n\t"
292 : "pushfl\n\t"
293 : "popl\t%0\n\t"
294 : "movl\t%0, %1\n\t"
295 : "xorl\t%2, %0\n\t"
296 : "pushl\t%0\n\t"
297 : "popfl\n\t"
298 : "pushfl\n\t"
299 : "popl\t%0\n\t"
300 : "popfl\n\t"
301 : : "=&r" (__eax), "=&r" (__ebx)
302 : : "i" (0x00200000));
303 : #endif
304 :
305 : if (__builtin_expect (!((__eax ^ __ebx) & 0x00200000), 0))
306 : return 0;
307 : #endif
308 :
309 : /* Host supports cpuid. Return highest supported cpuid input value. */
310 7227 : __cpuid (__ext, __eax, __ebx, __ecx, __edx);
311 :
312 7227 : if (__sig)
313 0 : *__sig = __ebx;
314 :
315 7227 : return __eax;
316 : }
317 :
318 : /* Return cpuid data for requested cpuid leaf, as found in returned
319 : eax, ebx, ecx and edx registers. The function checks if cpuid is
320 : supported and returns 1 for valid cpuid information or 0 for
321 : unsupported cpuid leaf. All pointers are required to be non-null. */
322 :
323 : static __inline int
324 4318 : __get_cpuid (unsigned int __leaf,
325 : unsigned int *__eax, unsigned int *__ebx,
326 : unsigned int *__ecx, unsigned int *__edx)
327 : {
328 4318 : unsigned int __ext = __leaf & 0x80000000;
329 4318 : unsigned int __maxlevel = __get_cpuid_max (__ext, 0);
330 :
331 4318 : if (__maxlevel == 0 || __maxlevel < __leaf)
332 0 : return 0;
333 :
334 4318 : __cpuid (__leaf, *__eax, *__ebx, *__ecx, *__edx);
335 4318 : return 1;
336 : }
337 :
338 : /* Same as above, but sub-leaf can be specified. */
339 :
340 : static __inline int
341 2909 : __get_cpuid_count (unsigned int __leaf, unsigned int __subleaf,
342 : unsigned int *__eax, unsigned int *__ebx,
343 : unsigned int *__ecx, unsigned int *__edx)
344 : {
345 2909 : unsigned int __ext = __leaf & 0x80000000;
346 2909 : unsigned int __maxlevel = __get_cpuid_max (__ext, 0);
347 :
348 2909 : if (__builtin_expect (__maxlevel == 0, 0) || __maxlevel < __leaf)
349 0 : return 0;
350 :
351 2909 : __cpuid_count (__leaf, __subleaf, *__eax, *__ebx, *__ecx, *__edx);
352 2909 : return 1;
353 : }
354 :
355 : static __inline void
356 : __cpuidex (int __cpuid_info[4], int __leaf, int __subleaf)
357 : {
358 : __cpuid_count (__leaf, __subleaf, __cpuid_info[0], __cpuid_info[1],
359 : __cpuid_info[2], __cpuid_info[3]);
360 : }
361 :
362 : #endif /* _CPUID_H_INCLUDED */
|
