Line data Source code
1 : /*-------------------------------------------------------------------------
2 : *
3 : * s_lock.h
4 : * Implementation of spinlocks.
5 : *
6 : * NOTE: none of the macros in this file are intended to be called directly.
7 : * Call them through the macros in spin.h.
8 : *
9 : * The following hardware-dependent macros must be provided for each
10 : * supported platform:
11 : *
12 : * void S_INIT_LOCK(slock_t *lock)
13 : * Initialize a spinlock (to the unlocked state).
14 : *
15 : * int S_LOCK(slock_t *lock)
16 : * Acquire a spinlock, waiting if necessary.
17 : * Time out and abort() if unable to acquire the lock in a
18 : * "reasonable" amount of time --- typically ~ 1 minute.
19 : * Should return number of "delays"; see s_lock.c
20 : *
21 : * void S_UNLOCK(slock_t *lock)
22 : * Unlock a previously acquired lock.
23 : *
24 : * void SPIN_DELAY(void)
25 : * Delay operation to occur inside spinlock wait loop.
26 : *
27 : * Note to implementors: there are default implementations for all these
28 : * macros at the bottom of the file. Check if your platform can use
29 : * these or needs to override them.
30 : *
31 : * Usually, S_LOCK() is implemented in terms of even lower-level macros
32 : * TAS() and TAS_SPIN():
33 : *
34 : * int TAS(slock_t *lock)
35 : * Atomic test-and-set instruction. Attempt to acquire the lock,
36 : * but do *not* wait. Returns 0 if successful, nonzero if unable
37 : * to acquire the lock.
38 : *
39 : * int TAS_SPIN(slock_t *lock)
40 : * Like TAS(), but this version is used when waiting for a lock
41 : * previously found to be contended. By default, this is the
42 : * same as TAS(), but on some architectures it's better to poll a
43 : * contended lock using an unlocked instruction and retry the
44 : * atomic test-and-set only when it appears free.
45 : *
46 : * TAS() and TAS_SPIN() are NOT part of the API, and should never be called
47 : * directly.
48 : *
49 : * CAUTION: on some platforms TAS() and/or TAS_SPIN() may sometimes report
50 : * failure to acquire a lock even when the lock is not locked. For example,
51 : * on Alpha TAS() will "fail" if interrupted. Therefore a retry loop must
52 : * always be used, even if you are certain the lock is free.
53 : *
54 : * It is the responsibility of these macros to make sure that the compiler
55 : * does not re-order accesses to shared memory to precede the actual lock
56 : * acquisition, or follow the lock release. Prior to PostgreSQL 9.5, this
57 : * was the caller's responsibility, which meant that callers had to use
58 : * volatile-qualified pointers to refer to both the spinlock itself and the
59 : * shared data being accessed within the spinlocked critical section. This
60 : * was notationally awkward, easy to forget (and thus error-prone), and
61 : * prevented some useful compiler optimizations. For these reasons, we
62 : * now require that the macros themselves prevent compiler re-ordering,
63 : * so that the caller doesn't need to take special precautions.
64 : *
65 : * On platforms with weak memory ordering, the TAS(), TAS_SPIN(), and
66 : * S_UNLOCK() macros must further include hardware-level memory fence
67 : * instructions to prevent similar re-ordering at the hardware level.
68 : * TAS() and TAS_SPIN() must guarantee that loads and stores issued after
69 : * the macro are not executed until the lock has been obtained. Conversely,
70 : * S_UNLOCK() must guarantee that loads and stores issued before the macro
71 : * have been executed before the lock is released.
72 : *
73 : * On most supported platforms, TAS() uses a tas() function written
74 : * in assembly language to execute a hardware atomic-test-and-set
75 : * instruction. Equivalent OS-supplied mutex routines could be used too.
76 : *
77 : *
78 : * Portions Copyright (c) 1996-2026, PostgreSQL Global Development Group
79 : * Portions Copyright (c) 1994, Regents of the University of California
80 : *
81 : * src/include/storage/s_lock.h
82 : *
83 : *-------------------------------------------------------------------------
84 : */
85 : #ifndef S_LOCK_H
86 : #define S_LOCK_H
87 :
88 : #ifdef FRONTEND
89 : #error "s_lock.h may not be included from frontend code"
90 : #endif
91 :
92 : #if defined(__GNUC__) || defined(__INTEL_COMPILER)
93 : /*************************************************************************
94 : * All the gcc inlines
95 : * Gcc consistently defines the CPU as __cpu__.
96 : * Other compilers use __cpu or __cpu__ so we test for both in those cases.
97 : */
98 :
99 : /*----------
100 : * Standard gcc asm format (assuming "volatile slock_t *lock"):
101 :
102 : __asm__ __volatile__(
103 : " instruction \n"
104 : " instruction \n"
105 : " instruction \n"
106 : : "=r"(_res), "+m"(*lock) // return register, in/out lock value
107 : : "r"(lock) // lock pointer, in input register
108 : : "memory", "cc"); // show clobbered registers here
109 :
110 : * The output-operands list (after first colon) should always include
111 : * "+m"(*lock), whether or not the asm code actually refers to this
112 : * operand directly. This ensures that gcc believes the value in the
113 : * lock variable is used and set by the asm code. Also, the clobbers
114 : * list (after third colon) should always include "memory"; this prevents
115 : * gcc from thinking it can cache the values of shared-memory fields
116 : * across the asm code. Add "cc" if your asm code changes the condition
117 : * code register, and also list any temp registers the code uses.
118 : *
119 : * If you need branch target labels within the asm block, include "%="
120 : * in the label names to make them distinct across multiple asm blocks
121 : * within a source file.
122 : *----------
123 : */
124 :
125 :
126 : #ifdef __i386__ /* 32-bit i386 */
127 :
128 : typedef unsigned char slock_t;
129 :
130 : #define TAS(lock) tas(lock)
131 :
132 : static inline int
133 : tas(volatile slock_t *lock)
134 : {
135 : slock_t _res = 1;
136 :
137 : /*
138 : * Use a non-locking test before asserting the bus lock. Note that the
139 : * extra test appears to be a small loss on some x86 platforms and a small
140 : * win on others; it's by no means clear that we should keep it.
141 : *
142 : * When this was last tested, we didn't have separate TAS() and TAS_SPIN()
143 : * macros. Nowadays it probably would be better to do a non-locking test
144 : * in TAS_SPIN() but not in TAS(), like on x86_64, but no-one's done the
145 : * testing to verify that. Without some empirical evidence, better to
146 : * leave it alone.
147 : */
148 : __asm__ __volatile__(
149 : " cmpb $0,%1 \n"
150 : " jne TAS%=_out \n"
151 : " lock \n"
152 : " xchgb %0,%1 \n"
153 : "TAS%=_out: \n"
154 : : "+q"(_res), "+m"(*lock)
155 : : /* no inputs */
156 : : "memory", "cc");
157 : return (int) _res;
158 : }
159 :
160 : #define SPIN_DELAY() spin_delay()
161 :
162 : static inline void
163 : spin_delay(void)
164 : {
165 : /*
166 : * This sequence is equivalent to the PAUSE instruction ("rep" is
167 : * ignored by old IA32 processors if the following instruction is
168 : * not a string operation); the IA-32 Architecture Software
169 : * Developer's Manual, Vol. 3, Section 7.7.2 describes why using
170 : * PAUSE in the inner loop of a spin lock is necessary for good
171 : * performance:
172 : *
173 : * The PAUSE instruction improves the performance of IA-32
174 : * processors supporting Hyper-Threading Technology when
175 : * executing spin-wait loops and other routines where one
176 : * thread is accessing a shared lock or semaphore in a tight
177 : * polling loop. When executing a spin-wait loop, the
178 : * processor can suffer a severe performance penalty when
179 : * exiting the loop because it detects a possible memory order
180 : * violation and flushes the core processor's pipeline. The
181 : * PAUSE instruction provides a hint to the processor that the
182 : * code sequence is a spin-wait loop. The processor uses this
183 : * hint to avoid the memory order violation and prevent the
184 : * pipeline flush. In addition, the PAUSE instruction
185 : * de-pipelines the spin-wait loop to prevent it from
186 : * consuming execution resources excessively.
187 : */
188 : __asm__ __volatile__(
189 : " rep; nop \n");
190 : }
191 :
192 : #endif /* __i386__ */
193 :
194 :
195 : #ifdef __x86_64__ /* AMD Opteron, Intel EM64T */
196 :
197 : typedef unsigned char slock_t;
198 :
199 : #define TAS(lock) tas(lock)
200 :
201 : /*
202 : * On Intel EM64T, it's a win to use a non-locking test before the xchg proper,
203 : * but only when spinning.
204 : *
205 : * See also Implementing Scalable Atomic Locks for Multi-Core Intel(tm) EM64T
206 : * and IA32, by Michael Chynoweth and Mary R. Lee. As of this writing, it is
207 : * available at:
208 : * http://software.intel.com/en-us/articles/implementing-scalable-atomic-locks-for-multi-core-intel-em64t-and-ia32-architectures
209 : */
210 : #define TAS_SPIN(lock) (*(lock) ? 1 : TAS(lock))
211 :
212 : static inline int
213 75701005 : tas(volatile slock_t *lock)
214 : {
215 75701005 : slock_t _res = 1;
216 :
217 75701005 : __asm__ __volatile__(
218 : " lock \n"
219 : " xchgb %0,%1 \n"
220 : : "+q"(_res), "+m"(*lock)
221 : : /* no inputs */
222 : : "memory", "cc");
223 75701005 : return (int) _res;
224 : }
225 :
226 : #define SPIN_DELAY() spin_delay()
227 :
228 : static inline void
229 311986 : spin_delay(void)
230 : {
231 : /*
232 : * Adding a PAUSE in the spin delay loop is demonstrably a no-op on
233 : * Opteron, but it may be of some use on EM64T, so we keep it.
234 : */
235 311986 : __asm__ __volatile__(
236 : " rep; nop \n");
237 311986 : }
238 :
239 : #endif /* __x86_64__ */
240 :
241 :
242 : /*
243 : * On ARM and ARM64, we use __sync_lock_test_and_set(int *, int) if available.
244 : *
245 : * We use the int-width variant of the builtin because it works on more chips
246 : * than other widths.
247 : */
248 : #if defined(__arm__) || defined(__aarch64__)
249 : #ifdef HAVE_GCC__SYNC_INT32_TAS
250 :
251 : #define TAS(lock) tas(lock)
252 :
253 : typedef int slock_t;
254 :
255 : static inline int
256 : tas(volatile slock_t *lock)
257 : {
258 : return __sync_lock_test_and_set(lock, 1);
259 : }
260 :
261 : #define S_UNLOCK(lock) __sync_lock_release(lock)
262 :
263 : #if defined(__aarch64__)
264 :
265 : /*
266 : * On ARM64, it's a win to use a non-locking test before the TAS proper. It
267 : * may be a win on 32-bit ARM, too, but nobody's tested it yet.
268 : */
269 : #define TAS_SPIN(lock) (*(lock) ? 1 : TAS(lock))
270 :
271 : #define SPIN_DELAY() spin_delay()
272 :
273 : static inline void
274 : spin_delay(void)
275 : {
276 : /*
277 : * Using an ISB instruction to delay in spinlock loops appears beneficial
278 : * on high-core-count ARM64 processors. It seems mostly a wash for smaller
279 : * gear, and ISB doesn't exist at all on pre-v7 ARM chips.
280 : */
281 : __asm__ __volatile__(
282 : " isb; \n");
283 : }
284 :
285 : #endif /* __aarch64__ */
286 : #endif /* HAVE_GCC__SYNC_INT32_TAS */
287 : #endif /* __arm__ || __aarch64__ */
288 :
289 :
290 : /* S/390 and S/390x Linux (32- and 64-bit zSeries) */
291 : #if defined(__s390__) || defined(__s390x__)
292 :
293 : typedef unsigned int slock_t;
294 :
295 : #define TAS(lock) tas(lock)
296 :
297 : static inline int
298 : tas(volatile slock_t *lock)
299 : {
300 : int _res = 0;
301 :
302 : __asm__ __volatile__(
303 : " cs %0,%3,0(%2) \n"
304 : : "+d"(_res), "+m"(*lock)
305 : : "a"(lock), "d"(1)
306 : : "memory", "cc");
307 : return _res;
308 : }
309 :
310 : #endif /* __s390__ || __s390x__ */
311 :
312 :
313 : #if defined(__sparc__) /* Sparc */
314 : /*
315 : * Solaris has always run sparc processors in TSO (total store) mode, but
316 : * linux didn't use to and the *BSDs still don't. So, be careful about
317 : * acquire/release semantics. The CPU will treat superfluous members as
318 : * NOPs, so it's just code space.
319 : */
320 :
321 : typedef unsigned char slock_t;
322 :
323 : #define TAS(lock) tas(lock)
324 :
325 : static inline int
326 : tas(volatile slock_t *lock)
327 : {
328 : slock_t _res;
329 :
330 : /*
331 : * "cas" would be better than "ldstub", but it is only present on
332 : * sparcv8plus and later, while some platforms still support sparcv7 or
333 : * sparcv8. Also, "cas" requires that the system be running in TSO mode.
334 : */
335 : __asm__ __volatile__(
336 : " ldstub [%2], %0 \n"
337 : : "=r"(_res), "+m"(*lock)
338 : : "r"(lock)
339 : : "memory");
340 : #if defined(__sparcv7) || defined(__sparc_v7__)
341 : /*
342 : * No stbar or membar available, luckily no actually produced hardware
343 : * requires a barrier.
344 : */
345 : #elif defined(__sparcv8) || defined(__sparc_v8__)
346 : /* stbar is available (and required for both PSO, RMO), membar isn't */
347 : __asm__ __volatile__ ("stbar \n":::"memory");
348 : #else
349 : /*
350 : * #LoadStore (RMO) | #LoadLoad (RMO) together are the appropriate acquire
351 : * barrier for sparcv8+ upwards.
352 : */
353 : __asm__ __volatile__ ("membar #LoadStore | #LoadLoad \n":::"memory");
354 : #endif
355 : return (int) _res;
356 : }
357 :
358 : #if defined(__sparcv7) || defined(__sparc_v7__)
359 : /*
360 : * No stbar or membar available, luckily no actually produced hardware
361 : * requires a barrier. We fall through to the default gcc definition of
362 : * S_UNLOCK in this case.
363 : */
364 : #elif defined(__sparcv8) || defined(__sparc_v8__)
365 : /* stbar is available (and required for both PSO, RMO), membar isn't */
366 : #define S_UNLOCK(lock) \
367 : do \
368 : { \
369 : __asm__ __volatile__ ("stbar \n":::"memory"); \
370 : *((volatile slock_t *) (lock)) = 0; \
371 : } while (0)
372 : #else
373 : /*
374 : * #LoadStore (RMO) | #StoreStore (RMO, PSO) together are the appropriate
375 : * release barrier for sparcv8+ upwards.
376 : */
377 : #define S_UNLOCK(lock) \
378 : do \
379 : { \
380 : __asm__ __volatile__ ("membar #LoadStore | #StoreStore \n":::"memory"); \
381 : *((volatile slock_t *) (lock)) = 0; \
382 : } while (0)
383 : #endif
384 :
385 : #endif /* __sparc__ */
386 :
387 :
388 : /* PowerPC */
389 : #if defined(__powerpc__) || defined(__powerpc64__)
390 :
391 : typedef unsigned int slock_t;
392 :
393 : #define TAS(lock) tas(lock)
394 :
395 : /* On PPC, it's a win to use a non-locking test before the lwarx */
396 : #define TAS_SPIN(lock) (*(lock) ? 1 : TAS(lock))
397 :
398 : /*
399 : * The second operand of addi can hold a constant zero or a register number,
400 : * hence constraint "=&b" to avoid allocating r0. "b" stands for "address
401 : * base register"; most operands having this register-or-zero property are
402 : * address bases, e.g. the second operand of lwax.
403 : *
404 : * NOTE: per the Enhanced PowerPC Architecture manual, v1.0 dated 7-May-2002,
405 : * an isync is a sufficient synchronization barrier after a lwarx/stwcx loop.
406 : * But if the spinlock is in ordinary memory, we can use lwsync instead for
407 : * better performance.
408 : */
409 : static inline int
410 : tas(volatile slock_t *lock)
411 : {
412 : slock_t _t;
413 : int _res;
414 :
415 : __asm__ __volatile__(
416 : " lwarx %0,0,%3,1 \n"
417 : " cmpwi %0,0 \n"
418 : " bne TAS%=_fail \n"
419 : " addi %0,%0,1 \n"
420 : " stwcx. %0,0,%3 \n"
421 : " beq TAS%=_ok \n"
422 : "TAS%=_fail: \n"
423 : " li %1,1 \n"
424 : " b TAS%=_out \n"
425 : "TAS%=_ok: \n"
426 : " lwsync \n"
427 : " li %1,0 \n"
428 : "TAS%=_out: \n"
429 : : "=&b"(_t), "=r"(_res), "+m"(*lock)
430 : : "r"(lock)
431 : : "memory", "cc");
432 : return _res;
433 : }
434 :
435 : /*
436 : * PowerPC S_UNLOCK is almost standard but requires a "sync" instruction.
437 : * But we can use lwsync instead for better performance.
438 : */
439 : #define S_UNLOCK(lock) \
440 : do \
441 : { \
442 : __asm__ __volatile__ (" lwsync \n" ::: "memory"); \
443 : *((volatile slock_t *) (lock)) = 0; \
444 : } while (0)
445 :
446 : #endif /* powerpc */
447 :
448 :
449 : #if defined(__mips__) && !defined(__sgi) /* non-SGI MIPS */
450 :
451 : typedef unsigned int slock_t;
452 :
453 : #define TAS(lock) tas(lock)
454 :
455 : /*
456 : * Original MIPS-I processors lacked the LL/SC instructions, but if we are
457 : * so unfortunate as to be running on one of those, we expect that the kernel
458 : * will handle the illegal-instruction traps and emulate them for us. On
459 : * anything newer (and really, MIPS-I is extinct) LL/SC is the only sane
460 : * choice because any other synchronization method must involve a kernel
461 : * call. Unfortunately, many toolchains still default to MIPS-I as the
462 : * codegen target; if the symbol __mips shows that that's the case, we
463 : * have to force the assembler to accept LL/SC.
464 : *
465 : * R10000 and up processors require a separate SYNC, which has the same
466 : * issues as LL/SC.
467 : */
468 : #if __mips < 2
469 : #define MIPS_SET_MIPS2 " .set mips2 \n"
470 : #else
471 : #define MIPS_SET_MIPS2
472 : #endif
473 :
474 : static inline int
475 : tas(volatile slock_t *lock)
476 : {
477 : volatile slock_t *_l = lock;
478 : int _res;
479 : int _tmp;
480 :
481 : __asm__ __volatile__(
482 : " .set push \n"
483 : MIPS_SET_MIPS2
484 : " .set noreorder \n"
485 : " .set nomacro \n"
486 : " ll %0, %2 \n"
487 : " or %1, %0, 1 \n"
488 : " sc %1, %2 \n"
489 : " xori %1, 1 \n"
490 : " or %0, %0, %1 \n"
491 : " sync \n"
492 : " .set pop "
493 : : "=&r" (_res), "=&r" (_tmp), "+R" (*_l)
494 : : /* no inputs */
495 : : "memory");
496 : return _res;
497 : }
498 :
499 : /* MIPS S_UNLOCK is almost standard but requires a "sync" instruction */
500 : #define S_UNLOCK(lock) \
501 : do \
502 : { \
503 : __asm__ __volatile__( \
504 : " .set push \n" \
505 : MIPS_SET_MIPS2 \
506 : " .set noreorder \n" \
507 : " .set nomacro \n" \
508 : " sync \n" \
509 : " .set pop " \
510 : : /* no outputs */ \
511 : : /* no inputs */ \
512 : : "memory"); \
513 : *((volatile slock_t *) (lock)) = 0; \
514 : } while (0)
515 :
516 : #endif /* __mips__ && !__sgi */
517 :
518 :
519 :
520 : /*
521 : * If we have no platform-specific knowledge, but we found that the compiler
522 : * provides __sync_lock_test_and_set(), use that. Prefer the int-width
523 : * version over the char-width version if we have both, on the rather dubious
524 : * grounds that that's known to be more likely to work in the ARM ecosystem.
525 : * (But we dealt with ARM above.)
526 : */
527 : #if !defined(TAS)
528 :
529 : #if defined(HAVE_GCC__SYNC_INT32_TAS)
530 :
531 : #define TAS(lock) tas(lock)
532 :
533 : typedef int slock_t;
534 :
535 : static inline int
536 : tas(volatile slock_t *lock)
537 : {
538 : return __sync_lock_test_and_set(lock, 1);
539 : }
540 :
541 : #define S_UNLOCK(lock) __sync_lock_release(lock)
542 :
543 : #elif defined(HAVE_GCC__SYNC_CHAR_TAS)
544 :
545 : #define TAS(lock) tas(lock)
546 :
547 : typedef char slock_t;
548 :
549 : static inline int
550 : tas(volatile slock_t *lock)
551 : {
552 : return __sync_lock_test_and_set(lock, 1);
553 : }
554 :
555 : #define S_UNLOCK(lock) __sync_lock_release(lock)
556 :
557 : #endif /* HAVE_GCC__SYNC_INT32_TAS */
558 :
559 : #endif /* !defined(TAS) */
560 :
561 :
562 : /*
563 : * Default implementation of S_UNLOCK() for gcc/icc.
564 : *
565 : * Note that this implementation is unsafe for any platform that can reorder
566 : * a memory access (either load or store) after a following store. That
567 : * happens not to be possible on x86 and most legacy architectures (some are
568 : * single-processor!), but many modern systems have weaker memory ordering.
569 : * Those that do must define their own version of S_UNLOCK() rather than
570 : * relying on this one.
571 : */
572 : #if !defined(S_UNLOCK)
573 : #define S_UNLOCK(lock) \
574 : do { __asm__ __volatile__("" : : : "memory"); *(lock) = 0; } while (0)
575 : #endif
576 :
577 : #endif /* defined(__GNUC__) || defined(__INTEL_COMPILER) */
578 :
579 :
580 : /*
581 : * ---------------------------------------------------------------------
582 : * Platforms that use non-gcc inline assembly:
583 : * ---------------------------------------------------------------------
584 : */
585 :
586 : #if !defined(TAS) /* We didn't trigger above, let's try here */
587 :
588 : #ifdef _MSC_VER
589 : typedef LONG slock_t;
590 :
591 : #define TAS(lock) (InterlockedCompareExchange(lock, 1, 0))
592 :
593 : #define SPIN_DELAY() spin_delay()
594 :
595 : #ifdef __aarch64__
596 : static __forceinline void
597 : spin_delay(void)
598 : {
599 : /*
600 : * Research indicates ISB is better than __yield() on AArch64. See
601 : * https://postgr.es/m/1c2a29b8-5b1e-44f7-a871-71ec5fefc120%40app.fastmail.com.
602 : */
603 : __isb(_ARM64_BARRIER_SY);
604 : }
605 : #elif defined(_WIN64)
606 : static __forceinline void
607 : spin_delay(void)
608 : {
609 : /*
610 : * If using Visual C++ on Win64, inline assembly is unavailable.
611 : * Use a _mm_pause intrinsic instead of rep nop.
612 : */
613 : _mm_pause();
614 : }
615 : #else
616 : static __forceinline void
617 : spin_delay(void)
618 : {
619 : /* See comment for gcc code. Same code, MASM syntax */
620 : __asm rep nop;
621 : }
622 : #endif
623 :
624 : #include <intrin.h>
625 :
626 : #ifdef __aarch64__
627 :
628 : /* _ReadWriteBarrier() is insufficient on non-TSO architectures. */
629 : #pragma intrinsic(_InterlockedExchange)
630 : #define S_UNLOCK(lock) _InterlockedExchange(lock, 0)
631 :
632 : #else
633 :
634 : #pragma intrinsic(_ReadWriteBarrier)
635 : #define S_UNLOCK(lock) \
636 : do { _ReadWriteBarrier(); (*(lock)) = 0; } while (0)
637 :
638 : #endif
639 : #endif
640 :
641 :
642 : #endif /* !defined(TAS) */
643 :
644 :
645 : /* Blow up if we didn't have any way to do spinlocks */
646 : #ifndef TAS
647 : #error PostgreSQL does not have spinlock support on this platform. Please report this to pgsql-bugs@lists.postgresql.org.
648 : #endif
649 :
650 :
651 : /*
652 : * Default Definitions - override these above as needed.
653 : */
654 :
655 : #if !defined(S_LOCK)
656 : #define S_LOCK(lock) \
657 : (TAS(lock) ? s_lock((lock), __FILE__, __LINE__, __func__) : 0)
658 : #endif /* S_LOCK */
659 :
660 : #if !defined(S_UNLOCK)
661 : /*
662 : * Our default implementation of S_UNLOCK is essentially *(lock) = 0. This
663 : * is unsafe if the platform can reorder a memory access (either load or
664 : * store) after a following store; platforms where this is possible must
665 : * define their own S_UNLOCK. But CPU reordering is not the only concern:
666 : * if we simply defined S_UNLOCK() as an inline macro, the compiler might
667 : * reorder instructions from inside the critical section to occur after the
668 : * lock release. Since the compiler probably can't know what the external
669 : * function s_unlock is doing, putting the same logic there should be adequate.
670 : * A sufficiently-smart globally optimizing compiler could break that
671 : * assumption, though, and the cost of a function call for every spinlock
672 : * release may hurt performance significantly, so we use this implementation
673 : * only for platforms where we don't know of a suitable intrinsic. For the
674 : * most part, those are relatively obscure platform/compiler combinations to
675 : * which the PostgreSQL project does not have access.
676 : */
677 : #define USE_DEFAULT_S_UNLOCK
678 : extern void s_unlock(volatile slock_t *lock);
679 : #define S_UNLOCK(lock) s_unlock(lock)
680 : #endif /* S_UNLOCK */
681 :
682 : #if !defined(S_INIT_LOCK)
683 : #define S_INIT_LOCK(lock) S_UNLOCK(lock)
684 : #endif /* S_INIT_LOCK */
685 :
686 : #if !defined(SPIN_DELAY)
687 : #define SPIN_DELAY() ((void) 0)
688 : #endif /* SPIN_DELAY */
689 :
690 : #if !defined(TAS_SPIN)
691 : #define TAS_SPIN(lock) TAS(lock)
692 : #endif /* TAS_SPIN */
693 :
694 :
695 : /*
696 : * Platform-independent out-of-line support routines
697 : */
698 : extern int s_lock(volatile slock_t *lock, const char *file, int line, const char *func);
699 :
700 : /* Support for dynamic adjustment of spins_per_delay */
701 : #define DEFAULT_SPINS_PER_DELAY 100
702 :
703 : extern void set_spins_per_delay(int shared_spins_per_delay);
704 : extern int update_spins_per_delay(int shared_spins_per_delay);
705 :
706 : /*
707 : * Support for spin delay which is useful in various places where
708 : * spinlock-like procedures take place.
709 : */
710 : typedef struct
711 : {
712 : int spins;
713 : int delays;
714 : int cur_delay;
715 : const char *file;
716 : int line;
717 : const char *func;
718 : } SpinDelayStatus;
719 :
720 : static inline void
721 66774 : init_spin_delay(SpinDelayStatus *status,
722 : const char *file, int line, const char *func)
723 : {
724 66774 : status->spins = 0;
725 66774 : status->delays = 0;
726 66774 : status->cur_delay = 0;
727 66774 : status->file = file;
728 66774 : status->line = line;
729 66774 : status->func = func;
730 66774 : }
731 :
732 : #define init_local_spin_delay(status) init_spin_delay(status, __FILE__, __LINE__, __func__)
733 : extern void perform_spin_delay(SpinDelayStatus *status);
734 : extern void finish_spin_delay(SpinDelayStatus *status);
735 :
736 : #endif /* S_LOCK_H */
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